FinFET isolation structure and method for fabricating the same

ABSTRACT

A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The first semiconductor fin is disposed on the semiconductor substrate, and the second semiconductor fin is disposed on the semiconductor substrate. The air gap is located between the first semiconductor fin and the second semiconductor fin, and the dielectric cap layer caps a top of the air gap.

RELATED APPLICATIONS

This application is a continuation of U.S. Non-provisional patent application Ser. No. 14/939,310 filed on Nov. 12, 2015, which is herein incorporated by reference.

BACKGROUND

When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, device packing density and device performance are challenged by device layout and isolation. In order to avoid leakage between neighboring devices (cells), the standard cell layout adopts dummy polycrystalline silicon (poly) segments formed on edges of a silicon oxide definition (OD) region such as an active region of a standard cell, i.e., poly-on-OD-edge (PODE).

As the semiconductor IC industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three-dimensional (3D) devices such fin-like field effect transistors (FinFETs). Advantages of FinFET devices include reducing the short channel effect and higher current flow. However, conventional FinFET devices and methods of fabricating FinFET devices have not been entirely satisfactory in adopting the PODE for isolating two neighboring devices (cells).

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a schematic three-dimensional diagram showing a semiconductor device in accordance with some embodiments of the present disclosure.

FIG. 1B is a schematic top view of the semiconductor device shown in FIG. 1A.

FIG. 1C to FIG. 1F are schematic cross-sectional views showing various types of fin isolation structure for the semiconductor device viewed along line A1-A1′ in FIG. 1A.

FIG. 2A and FIG. 2B are schematic three-dimensional diagrams of intermediate stages showing a method for fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

FIG. 2C to FIG. 2G are schematic cross-sectional views of intermediate stages showing a method for fabricating the semiconductor device viewed along line B1-B1′ in FIG. 2B in accordance with some embodiments of the present disclosure.

FIG. 2F′ and FIG. 2G′ are schematic cross-sectional views of intermediate stages showing a method for fabricating the semiconductor device viewed along line B1-B1′ in FIG. 2B in accordance with certain embodiments of the present disclosure.

FIG. 3 is a flow chart showing a method for fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “bottom”, “top” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments of the present disclosure are directed to fin-like field-effect transistor (FinFET) devices between which a fin isolation structure is disposed as a PODE for preventing leakage between neighboring devices (cells). The PODE helps to achieve better device performance and better poly profile control. The fin isolation structure has an air gap in a semiconductor fin to separate two neighboring cells, and a dielectric cap layer to cap a top of the air gap for subsequent processes such as metal landing. The air gap has a very low dielectric constant, and is an excellent electrical isolator. Because the air gap is formed within the semiconductor fin, no additional area is needed to form the fin isolation structure, and thus the device size can be shrunk.

Referring to FIG. 1A and FIG. 1B, FIG. 1A is a schematic three-dimensional diagram of a semiconductor device 100 in accordance with some embodiments of the present disclosure, and FIG. 1B is a schematic top view of the semiconductor device 100 shown in FIG. 1A. The semiconductor device 100 includes a semiconductor substrate 110, a stop layer 112 on the semiconductor substrate 110, a semiconductor fin 120 on the stop layer 112, gate structures 130 a and 130 b crossing over the semiconductor fin 120, and dummy gate structures 140 a, 140 b and 140 c crossing over the semiconductor fin 120. The semiconductor substrate 110 is defined as any construction including semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. The stop layer 112 includes, but is not limited to, SiGeO_(x), SiGe, SiO_(x), SiP or SiPO_(x), where x is greater than 0. The stop layer 112 has a thickness in a range from about 1 nm to about 50 nm. The semiconductor fin 120 protrudes from the semiconductor substrate 110. For forming the semiconductor fin 120, a semiconductor layer may be formed on the semiconductor substrate 110 and is etched until the stop layer 112 is exposed. Because the etching stops at the top of the stop layer 112, a height of the semiconductor fin 120 is approximately equal to a thickness of the semiconductor layer, such that the thickness of the semiconductor layer can be well controlled. Consequently, the height of the semiconductor fin 120, and thus the channel width of the FinFET (semiconductor device 100) can be well controlled in view of the requirements of circuit design, thereby obtaining good device performance.

The gate structures 130 a and 130 b may be referred herein as functional or operational gate structures. As shown in FIG. 1B, a cell A and a cell B abutting the cell A are disposed on the semiconductor fin 120. The dummy gate structures 140 a and 140 b are used to cover and protect the ends of the semiconductor fin 120 of the cell A during processing, and the dummy gate structures 140 b and 140 c are used to cover and protect the ends of the semiconductor fin 120 of the cell B during processing, thereby providing additional reliability during processing. That is, the dummy gate structures 140 a, 140 b and 140 c are not electrically connected as gates for FinFET devices, and have no function in the circuit. Each of the dummy gate structures 140 a, 140 b and 140 c has a fin isolation structure 150. The cell A is electrically isolated from the cell B by the fin isolation structure 150 of the dummy gate structures 140 b which acts as a PODE for preventing leakage between the cell A and the cell B. In some embodiments, another cell may be connected to the cell A through the dummy gate structure 140 a, and another cell may be connected to the cell B through the dummy gate structure 140 c.

It is noted that embodiments of the present disclosure are also applicable to only the cell A or the cell B, i.e. to a semiconductor fin with only the cell A or the cell B, in which two opposite ends of the semiconductor fin have the fin isolation structures respectively.

Because the dummy gate structures 140 a, 140 b and 140 c have the same structure, the dummy gate structure 140 b is used herein as an example for explaining the details of the fin isolation structure 150. As shown in FIG. 1B, the semiconductor fin 120 at the dummy gate structure 140 b has the fin isolation structure 150 at a common boundary that is shared by the two cells A and B. Referring to FIG. 1C, FIG. 1C is a schematic cross-sectional view showing a type of the fin isolation structure 150 for the semiconductor device 100 viewed along line A1-A1′ in FIG. 1A. As shown in FIG. 1C, the fin isolation structure 150 has an air gap 152 dividing the semiconductor fin 120 into two portions 120 a and 120 b of the semiconductor fin 120 (also referred to as a first semiconductor fin 120 a and a second semiconductor fin 120 b). The air gap 152 extends to the stop layer 112 from tops of two portions 120 a and 120 b of the semiconductor fin 120. The air gap 152 has a very low dielectric constant and is an excellent electrical isolator, such that leakage between the cell A and the cell B can be avoided with a small width of the air gap 152. In some embodiments, the two portions 120 a and 120 b of the semiconductor fin 120 are spaced at a distance D1 (the width of the air gap 152) in a range from about 5 nm to about 50 nm, and the claimed scope of the present disclosure is not limited in this respect. Because the air gap 152 is formed within the semiconductor fin 120, no additional area is needed to form the fin isolation structure 150, and thus the device size can be shrunk.

The fin isolation structure 150 includes a dummy gate dielectric 142 a on the portion 120 a, a dummy gate dielectric 142 b on the portion 120 b, a dummy gate spacer 144 a on the dummy gate dielectric 142 a, a dummy gate spacer 144 b on the dummy gate dielectric 142 b, and a dielectric cap layer 154 sandwiched between the dummy gate spacer 144 a and the dummy gate spacer 144 b. The dielectric cap layer 154 can be used as a support for subsequent processes such as metal landing. Only a relatively small thickness T1 of the dielectric cap layer 154 is needed as long the dielectric cap layer 154 is strong enough to support the elements to be implemented in the subsequent processes. Thus, the dielectric constant of the area between the two portions 120 a and 120 b of the semiconductor fin 120 can be kept as small as possible, because the air gap 152 occupies a large part of the area between the two portions 120 a and 120 b. In some embodiments, the dielectric cap layer 154 has the thickness T1 extending from top surfaces of the dummy gate spacer 144 a and 144 b towards the semiconductor substrate 110, in which the thickness T1 is smaller than a height P1 of each of the dummy gate spacers 144 a and 144 b. The dielectric cap layer 154 may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like. In addition, the top surface of the dielectric cap layer 154 may be flat and coplanar with the top surfaces of the dummy gate spacers 144 a and 144 b, thereby facilitating the subsequent processes.

In some embodiments, each of the dummy gate spacers 144 a and 144 b includes a dielectric material, such as silicon nitride, silicon carbide, silicon oxynitride, other suitable materials, and/or combinations, but embodiments of the present disclosure are not limited thereto. In some embodiments, each of the dummy gate dielectrics 142 a and 142 b may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. In other embodiments, the dummy gate dielectric 142 includes dielectric materials having a high dielectric constant (k value), for example, greater than 3.9. The materials may include silicon nitrides, oxynitrides, metal oxides such as HfO₂, HfZrO_(x), HfSiO_(x), HfTiO_(x), HfAlO_(x), the like, or combinations and multi-layers thereof.

The semiconductor device 100 may further include epitaxial layers 122 a and 122 b on the semiconductor substrate 110. The epitaxial layers 122 a is located at one side of the two portions 120 a and 120 b of the semiconductor fin 120, and is a source/drain portion of the cell A. The epitaxial layer 122 b is located at the other side of the two portions 120 a and 120 b of the semiconductor fin 120, and is a source/drain portion of the cell B. The epitaxial layers 122 a and 122 b may be doped by performing an implanting process to implant appropriate dopants to complement the dopants in the semiconductor fin 120. In some embodiments, the epitaxial layers 122 a and 122 b may be formed by forming recesses (not shown) in the semiconductor fin 120 and epitaxially growing material in the recesses. The epitaxial layers 122 a and 122 b may be doped either through an implantation method as discussed above, or else by in-situ doping as the material is grown. The semiconductor device 100 may further include dielectric layers 146 a and 146 b respectively on the epitaxial layers 122 a and 122 b, in which the dielectric layers 146 a and 146 b sandwich the dummy gate spacers 144 a and 144 b and the dielectric cap layer 154. The dielectric layers 146 a and 146 b may include silicon nitride (SiN), silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like.

Embodiments of the present disclosure further provide several types of fin isolation structure 150 hereinafter. Referring to FIG. 1D, FIG. 1D is a schematic cross-sectional view showing another type of fin isolation structure 150 for the semiconductor device 100 viewed along line A1-A1′ in FIG. 1A. As shown in FIG. 1D, the fin isolation structure 150 has a first air gap 152 a on the stop layer 112, and a second air gap 152 b above the first air gap 152 a. The first air gap 152 a has a trapezoidal cross-section, and the second air gap 152 b has a rectangular cross-section, i.e. a width D2 of a bottom of the first air gap 152 a is greater than a width D1 of a bottom of the second air gap 152 b. The ratio of the height H2 of the second air gap 152 b and the dielectric cap layer 154 to the total height H1 of the first air gap 152 a, the second air gap 152 b and the dielectric cap layer 154 is in a range from about 0.05 to about 1. The first air gap 152 a and the second air gap 152 b divide the semiconductor fin 120 into two portions 120 a and 120 b of the semiconductor fin 120. The first air gap 152 a, the second air gap 152 b and the dielectric cap layer 154 have low dielectric constants and are excellent electrical isolators, such that leakage between the cell A and the cell B can be avoided with small widths of the first air gap 152 a, the second air gap 152 b and the dielectric cap layer 154. In some embodiments, the two portions 120 a and 120 b of the semiconductor fin 120 are spaced at a distance D1 (the width of the dielectric cap layer 154) in a range from about 5 nm to about 50 nm, and the claimed scope of the present disclosure is not limited in this respect. Because the first air gap 152 a, the second air gap 152 b and the dielectric cap layer 154 are formed within the semiconductor fin 120, no additional area is needed to form the fin isolation structure 150, and thus the device size can be shrunk.

Referring to FIG. 1E, FIG. 1E is a schematic cross-sectional view showing another type of fin isolation structure 150 for the semiconductor device 100 viewed along line A1-A1′ in FIG. 1A. As shown in FIG. 1E, the fin isolation structure 150 has an air gap 152 c extending into a portion of the semiconductor substrate 110 through the stop layer 112 for a depth L1. The ratio of the depth L1 to the height H3 of the air gap 152 c and the dielectric cap layer 154 is in a range from about 0.05 to about 1. The air gap 152 c divides the semiconductor fin 120 into two portions 120 a and 120 b of the semiconductor fin 120. The air gap 152 c and the dielectric cap layer 154 have low dielectric constants and are excellent electrical isolators, such that leakage between the cell A and the cell B can be avoided with small widths of the air gap 152 c and the dielectric cap layer 154. In some embodiments, the two portions 120 a and 120 b of the semiconductor fin 120 are spaced at a distance D1 (the width of the dielectric cap layer 154) in a range from about 5 nm to about 50 nm, and the claimed scope of the present disclosure is not limited in this respect. Because the air gap 152 c and the dielectric cap layer 154 are formed within the semiconductor fin 120, no additional area is needed to form the fin isolation structure 150, and thus the device size can be shrunk.

Referring to FIG. 1F, FIG. 1F is a schematic cross-sectional view showing another type of fin isolation structure 150 for the semiconductor device 100 viewed along line A1-A1′ in FIG. 1A. As shown in FIG. 1F, the fin isolation structure 150 has an air gap 152 d extending into a portion of the semiconductor substrate 110 through the stop layer 112 for a depth L2. The air gap 152 d has a flat bottom enclosed by an arc surface, in which a width D3 of the flat bottom of the air gap 152 d is smaller than a width D1 of the dielectric cap layer 154. The ratio of the depth L2 to the height H4 of the air gap 152 d and the dielectric cap layer 154 is in a range from about 0.01 to about 1. The air gap 152 d divides the semiconductor fin 120 into two portions 120 a and 120 b of the semiconductor fin 120. The air gap 152 d and the dielectric cap layer 154 have low dielectric constants and are excellent electrical isolators, such that leakage between the cell A and the cell B can be avoided with small widths of the air gap 152 d and the dielectric cap layer 154. In some embodiments, the two portions 120 a and 120 b of the semiconductor fin 120 are spaced at a distance D1 (the width of the dielectric cap layer 154) in a range from about 5 nm to about 50 nm, and the claimed scope of the present disclosure is not limited in this respect. Because the air gap 152 d and the dielectric cap layer 154 are formed within the semiconductor fin 120, no additional area is needed to form the fin isolation structure 150, and thus the device size can be shrunk.

Referring to FIG. 2A to FIG. 2G, FIG. 2A and FIG. 2B are schematic three-dimensional diagrams of intermediate stages showing a method for fabricating a semiconductor device 200 in accordance with some embodiments of the present disclosure, and FIG. 2C to FIG. 2G are schematic cross-sectional views of intermediate stages showing a method for fabricating the semiconductor device 200 viewed along line B1-B1′ in FIG. 2B in accordance with some embodiments of the present disclosure.

As shown in FIG. 2A, a semiconductor substrate 210 is provided, and a stop layer 212 is formed on the semiconductor substrate 210 by, for example, implantation or atomic layer deposition (ALD). Then, a Si layer (not shown) is epitaxially grown on the stop layer 212, and is patterned and etched using a photolithography technique to form a semiconductor fin 220. The semiconductor substrate 210 is defined as any construction including semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. The stop layer 212 is formed from, but is not limited to, SiGeO_(x), SiGe, SiO_(x), SiP or SiPO_(x), where x is greater than 0. The stop layer 212 has a thickness in a range from about 1 nm to about 50 nm. In some embodiments, a layer of photoresist material (not shown) is deposited over the Si layer, and is irradiated (exposed) in accordance with a desired pattern and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from subsequent processing operation, such as etching. It should be noted that other masks, such as an oxide or silicon nitride mask, may also be used in the etching process. A mask may be used to control the shape of the semiconductor fin 220 during the epitaxial growth process.

As shown in FIG. 2B, gate structures 230 a, 230 b, 230 c, 230 d and 230 c are formed to cross over the semiconductor fin 220, in which the gate structures 230 b and 230 d are functional or operational gate structures, and the gate structures 230 a, 230 c and 230 e will be processed later to become dummy gate structures. A cell A and a cell B abutting the cell A are defined on the semiconductor fin 220. The dummy gate structures (gate structures 230 a and 230 c) are used to cover and protect the ends of the semiconductor fin 220 of the cell A during processing, and the dummy gate structures (gate structures 230 c and 230 e) are used to cover and protect the ends of the semiconductor fin 220 of the cell B during processing, thereby providing additional reliability during processing. That is, the (dummy) gate structures 230 a, 230 c and 230 e will be processed later to have no function in the circuit. At this time, the gate structures 230 a, 230 b, 230 c, 230 d and 230 c have the same structures, and thus the gate structure 230 c is used herein as an example for explaining the details thereof.

As shown in FIG. 2C, a gate dielectric 242 is formed on the semiconductor fin 220. The gate dielectric 242, which prevents electron depletion, may include, for example, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof. Some embodiments may include hafnium oxide (HfO₂) hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta₂O₅), yttrium oxide (Y₂O₃), strontium titanium oxide (SrTiO₃, STO), barium titanium oxide (BaTiO₃, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al₂O₃), silicon nitride (Si₃N₄), oxynitrides (SiON), and combinations thereof. The gate dielectric 242 may have a multilayer structure such as one layer of silicon oxide (e.g., interfacial layer) and another layer of high-k material. The gate dielectric 242 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, ozone oxidation, other suitable processes, or combinations thereof.

As shown in FIG. 2C, a gate conductor (also referred to as a dummy gate) 248 and a gate spacer 244 are formed on the gate dielectric 242, in which the gate spacer 244 peripherally enclosing the gate conductor 248. The gate conductor 248 may be formed from a conductive material and may be selected from a group consisting of polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, metals, their combinations, and the like. Examples of metallic nitrides include tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride, or their combinations. Examples of metallic silicide include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or their combinations. Examples of metallic oxides include ruthenium oxide, indium tin oxide, or their combinations. Examples of metal include tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, etc. The gate conductor 248 may be deposited by chemical vapor deposition (CVD), sputter deposition, or other techniques known and used in the art for depositing conductive materials.

As shown in FIG. 2C, epitaxial layers 222 a and 222 b are formed on the stop layer 212. The epitaxial layer 222 a is formed at one side of the semiconductor fin 220, and is a source/drain portion of the cell A. The epitaxial layer 222 b is formed at the other side of the semiconductor fin 220, and is a source/drain portion of anther cell B abutting the cell A. The epitaxial layers 222 a and 222 b may be doped by performing an implanting process to implant appropriate dopants to complement the dopants in the semiconductor fin 220. In some embodiments, the epitaxial layers 222 a and 222 b may be formed by forming recesses (not shown) in the semiconductor fin 120 and epitaxially growing material in the recesses. The epitaxial layers 222 a and 222 b may be doped either through an implantation method as discussed above, or else by in-situ doping as the material is grown. Dielectric layers 246 a and 246 b may be formed respectively on the epitaxial layers 222 a and 222 b, in which the dielectric layers 246 a and 246 b sandwich the gate spacer 244. The dielectric layers 246 a and 246 b may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like and may be formed by methods utilized to form such a layer, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputter, and other methods known in the art.

Then, while the gate structures 230 b and 230 d are used as functional or operational gate structures for the cell A and the cell B, the gate structures 230 a, 230 c and 230 e are further processed in the subsequent operations to become dummy gate structures each of which has a fin isolation structure for isolating the cell A and the cell B.

As shown in FIG. 2D, a photoresist 250 is formed and patterned over the gate conductor 248, the gate spacer 244 and the dielectric layers 246 a and 246 b. In some embodiments, the photoresist 250 is formed by depositing, exposing, and developing a layer of photoresist material. The photoresist 250 is patterned to expose the gate conductor 248. The gate conductor 248 may be removed by suitable wet or dry etching processes. For example, an etching solution such as, for example, NH₄OH, dilute-HF, and/or other suitable etchant may be used. Then, the photoresist 250 is removed to obtain a structure as shown in FIG. 2E.

Thereafter, as shown in FIG. 2F, an exposed portion of the gate dielectric 242 and the underlying semiconductor fin 220 are etched to form an air gap (opening) 252 by using the gate spacer 244 as a mask. The gate dielectric 242 and the semiconductor fin 220 may be etched using reactive ion etch (RIE) and/or other suitable processes. Numerous other embodiments of methods to form the air gap (opening) 252 may be suitable. The air gap 252 divides the semiconductor fin 220 into two portions 220 a and 220 b of the semiconductor fin 220 and ends on the stop layer 212. Then, as shown in FIG. 2G, a dielectric cap layer 254 is formed between the dummy gate spacer 244 a and the dummy gate spacer 244 b. The dielectric cap layer 254 caps a top of the air gap 252, and is used as a support for subsequent processes such as metal landing. Only a small thickness of the dielectric cap layer 254 is needed, as long the dielectric cap layer 254 is strong enough to support the elements to be implemented in the subsequent processes. Thus, the dielectric constant of the area between the two portions 220 a and 220 b of the semiconductor fin 220 can be kept as small as possible, because the air gap 252 occupies a large part of the area between the two portions 220 a and 220 b. The dielectric cap layer 254 may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like and may be formed by methods utilized to form such a layer, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputter, and other methods known in the art.

Referring to FIG. 2F′ and FIG. 2G′, FIG. 2F′ and FIG. 2G′ are schematic cross-sectional views of intermediate stages showing a method for fabricating the semiconductor device viewed along line B1-B1′ in FIG. 2B in accordance with certain embodiments of the present disclosure. In certain embodiments, the stop layer 212 underlying the semiconductor fin 220 is also etched, such that the air gap 252 extends to a portion of the semiconductor substrate 210 through the stop layer 212 from tops of two portions 220 a and 220 b of the semiconductor fin 220. The larger depth into the semiconductor substrate 210 can achieve higher performance in terms of leakage current for the cells A and B. The stop layer 212 may be etched by using C_(x)F_(y), NF_(x), N₂, O₂, Cl₂, Ar, SF_(x), C_(x)H_(y)F_(z) or HBr as an etchant, where x and y are greater than 0.

Then, as shown in FIG. 2G′, the dielectric cap layer 254 fills the air gap 252, and is used as a support for subsequent processes such as metal landing. Because the dielectric cap layer 254 and the air gap 252 have low dielectric constants, and are excellent electrical isolators, such that leakage between the cell A and the cell B can be avoided even with small widths of the dielectric cap layer 254 and the air gap 252. In some embodiments, the two portions 220 a and 220 b of the semiconductor fin 220 are spaced at a distance in a range from about 5 nm to about 50 nm, and the claimed scope of the present disclosure is not limited in this respect. Because the dielectric cap layer 254 and the air gap 252 are formed within the semiconductor fin 220, no additional area is needed to form the fin isolation structure, and thus the device size can be shrunk.

It is noted that the air gap 252 may be formed with different cross-sectional profiles. In some examples, the air gap 252 may include a first air gap on the stop layer 212, and a second air gap above the first air gap, in which the first air gap has a trapezoidal cross-section, and the second air gap has a rectangular cross-section, as shown in FIG. 1D. In certain examples, the air gap 252 may be formed with a flat bottom enclosed by an arc surface, as shown in FIG. 1F.

Referring to FIG. 3 and FIG. 2A to FIG. 2F, FIG. 3 is a flow chart showing a method for fabricating the semiconductor device 200 in accordance with some embodiments of the present disclosure. The method begins at operation 306, where a stop layer 212 is formed on a semiconductor fin 220, as shown in FIG. 2A. Then, at operation 310, a semiconductor fin 220 is formed on the stop layer 212, as shown in FIG. 2A. At operation 320, two cells A and B adjacent to each other are formed on the semiconductor fin 220, as shown in FIG. 2B. Gate structures 230 a, 230 b, 230 c, 230 d and 230 c are formed to cross over the semiconductor fin 220. The gate structure 230 b is a functional or operational gate structure for the cell A, and the gate structures 230 a and 230 c will be processed in operations 350 and 360 to become dummy gate structures acting as PODEs for protecting the ends of the semiconductor fin 220 of the cell A during processing. The gate structure 230 d is a functional or operational gate structure for the cell B, and the gate structures 230 c and 230 e will be processed in operations 350 and 360 to become dummy gate structures acting as PODEs for protecting the ends of the semiconductor fin 220 of the cell B during processing. The gate structure 230 c acts as the PODE for preventing leakage between the cell A and the cell B.

At operation 330, a gate conductor 248 of the gate structure 230 c is formed on a top of the semiconductor fin 220 at a common boundary that is shared by the two cells A and B, as shown in FIG. 2C. At operation 340, a gate spacer 244 peripherally enclosing the gate conductor 248 is formed on the semiconductor fin 220, as shown in FIG. 2C. At operation 350, the gate conductor 248 and the semiconductor fin 220 are etched to form an air gap 252, thereby dividing the semiconductor fin 220 into two portions 220 a and 220 b of the semiconductor fin, as shown in FIG. 2D to FIG. 2F. In some embodiments, the gate conductor 248, the semiconductor fin 220, the stop layer 212 and a portion of the semiconductor substrate 210 are etched to form an air gap 252, as shown in FIG. 2D and FIG. 2E′ to FIG. 2F′. At operation 360, a dielectric cap layer 254 is deposited into the air gap 252 to cap a top of the air gap 242, as shown in FIG. 2G or FIG. 2G′. The dielectric cap layer 254 may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like and may be formed by methods utilized to form such a layer, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputter, and other methods known in the art. The dielectric cap layer 254 is used as a support for subsequent processes such as metal landing. The air gap 252 with the dielectric cap layer 254 is used for preventing leakage between the cell A and the cell B. At operation 370, an epitaxial layer 222 a or 222 b is formed at one side of each of the two portions 220 a and 220 b of the semiconductor fin 220, as shown in FIG. 2G. The epitaxial layers 222 a is a source/drain portion of the cell A, and the epitaxial layer 222 b is a source/drain portion of anther cell B abutting the cell A.

In accordance with an embodiment of the present disclosure, the present disclosure discloses a semiconductor device including a semiconductor substrate, a first semiconductor fin on the semiconductor substrate, a second semiconductor fin on the semiconductor substrate, an air gap between the first semiconductor fin and the second semiconductor fin, and a dielectric cap layer capping a top of the air gap.

In accordance with another embodiment of the present disclosure, the present disclosure discloses a semiconductor device including a semiconductor substrate, a stop layer a stop layer on the semiconductor substrate, a first semiconductor fin on the stop layer, a second semiconductor fin on the stop layer, a first dummy gate spacer on the first semiconductor fin, a second dummy gate spacer on the second semiconductor fin, and a dielectric cap layer between the first dummy gate spacer and the second dummy gate spacer, in which a bottom of the dielectric cap layer is separated from the stop layer.

In accordance with yet another embodiment, the present disclosure discloses a method for forming a semiconductor device. In this method, a dummy gate is formed at least on a top of a semiconductor fin. At least one dummy gate spacer is formed on at least one sidewall of the dummy gate. The dummy gate and the semiconductor fin are etched to form an air gap dividing the semiconductor fin into first and second portions. A dielectric cap layer is formed into the air gap to cap a top of the air gap.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor device, comprising: a semiconductor substrate; a first semiconductor fin on the semiconductor substrate; a second semiconductor fin on the semiconductor substrate; an air gap between the first semiconductor fin and the second semiconductor fin; a dielectric cap layer capping a top of the air gap; and two dummy gate spacers respectively on the first semiconductor fin and the second semiconductor fin, and sandwiching the dielectric cap layer.
 2. The semiconductor device of claim 1, wherein the first semiconductor fin and the second semiconductor fin are spaced at a distance substantially in a range from 5 nm to 50 nm.
 3. The semiconductor device of claim 1, wherein the dielectric cap layer comprises silicon oxide or silicon nitride.
 4. The semiconductor device of claim 1, further comprising: a stop layer disposed between the semiconductor substrate, and the first semiconductor fin and the second semiconductor fin.
 5. The semiconductor device of claim 4, wherein the stop layer comprises SiGeO_(x), SiGe, SiO_(x), SiP or SiPO_(x), where x is greater than
 0. 6. The semiconductor device of claim 4, wherein the stop layer has a thickness substantially in a range from 1 nm to 50 nm.
 7. The semiconductor device of claim 4, wherein the air gap has a first air gap on the stop layer, and a second air gap above the first air gap, and a width of a bottom of the first air gap is greater than a width of a bottom of the second air gap.
 8. The semiconductor device of claim 4, where the air gap extends from tops of the first semiconductor fin and the second semiconductor fin to a portion of the semiconductor substrate through the stop layer.
 9. The semiconductor device of claim 1, wherein the air gap has a flat bottom enclosed by an arc surface, and a width of the flat bottom of the air gap is smaller than a width of a top of the dielectric cap layer.
 10. The semiconductor device of claim 1, wherein the air gap extends between a portion of the dummy gate spacers.
 11. The semiconductor device of claim 1, comprising: an epitaxial layer, wherein the epitaxial layer is spaced apart from the air gap by the first semiconductor fin.
 12. A semiconductor device, comprising: a semiconductor substrate; a stop layer on the semiconductor substrate; a first semiconductor fin on the stop layer; a second semiconductor fin on the stop layer; a first dummy gate spacer overlying the first semiconductor fin; a second dummy gate spacer overlying the second semiconductor fin; and a dielectric cap layer between the first dummy gate spacer and the second dummy gate spacer, wherein a bottom of the dielectric cap layer is separated from the stop layer.
 13. The semiconductor device of claim 12, wherein the first semiconductor fin and the second semiconductor fin are spaced at a distance substantially in a range from 5 nm to 50 nm.
 14. The semiconductor device of claim 12, wherein the stop layer has a thickness substantially in a range from 1 nm to 50 nm.
 15. A method for forming a semiconductor device, the method comprising: forming a dummy gate at least on a top of a semiconductor fin; forming at least one dummy gate spacer on at least one sidewall of the dummy gate; etching the dummy gate and the semiconductor fin to form an air gap dividing the semiconductor fin into first and second portions; and forming a dielectric cap layer into the air gap to cap a top of the air gap.
 16. The method of claim 15, further comprising: forming a stop layer between a semiconductor substrate and the semiconductor fin.
 17. The method of claim 16, wherein etching the dummy gate and the semiconductor fin further etches the stop layer and a portion of semiconductor fin.
 18. The method of claim 16, wherein an operation of etching etches the stop layer by using C_(x)F_(y), NF_(x), N₂, O₂, CL₂, Ar, SF_(x), C_(x)H_(y)F_(z) or HBr as an etchant, where x and y are greater than
 0. 19. The method of claim 16, wherein forming the stop layer is performed by implantation or atomic layer deposition (ALD).
 20. The method of claim 15, wherein forming the dielectric cap layer is performed using silicon oxide or silicon nitride. 